Trade-off
Relationship between Breakdown and Gate-Lag in Recessed-Gate GaAs FETs
Y. Mitani, D.
Faculty of Systems
Engineering, Shibaura Institute of Technology
307 Fukasaku, Saitama
330-8570,
Keywords: GaAs MESFET,
breakdown, gate-lag, recessed-gate structure, surface state, impact ionization
Abstract
Breakdown characteristics
of recessed-gate GaAs MESFETs are studied by two-dimensional analysis including
surface states and impact ionization of carriers. It is shown that the
breakdown voltage could be rather lowered when introducing a
narrowly-recessed-gate structure. Recess-parameter dependence of gate-lag (or
slow current transients during turn-on) is also analyzed. It is shown that
there may be a trade-off relationship between raising the breakdown voltage and
reducing the gate-lag.