Conference Information

2006 International Conference on
Compound Semiconductor Manufacturing Technology
April 24-27, 2006

Vancouver as viewed from Grouse Mountain. Courtesy of Tourism
Vancouver/Al Harvey.

MESSAGE FROM THE CONFERENCE CHAIR:
On behalf of the Technical Program Committee, I invite you to attend the 21^st annual International Conference on Compound Semiconductor Manufacturing Technology. CS MANTECH will be held at The Fairmont Hotel Vancouver in Vancouver, British Columbia, Canada from April 25 - 27, 2006, with a workshop on April 24, 2006.

Each year, the CS MANTECH Conference provides a forum for sharing information on manufacturing technology and practices in an open and informal environment. To ensure that our technical program covers the practices, trends, and challenges of our dynamic industry, we have invited representatives from different sectors of the industry to serve on the Technical Program Committee (TPC). This committee currently consists of over 70 volunteers from a broad spectrum of companies across our industry, research laboratories, and funding agencies. The TPC has put together a very interesting and varied program of papers and topics covering the details of manufacturing, as well as technology trends and emerging technologies, reflecting up-to-date directions and practices.

In addition to the technical presentations, CS MANTECH offers a wide range of events such as the Workshop, Exhibits, Exhibitors’ Forum, and Panel and Rump Sessions. We also host an Exhibits Reception, the International Reception, and the Interactive Forum. These events are designed to maximize the opportunities for the exchange of information, and for networking and informal interactions between delegates. In the pages of this Advance Program you will find more details concerning these events.

We urge anyone associated with compound semiconductor manufacturing to attend the conference and update their skills and knowledge base. Every year the organizing committee strives to provide the best possible conference, and every year, thanks to its efforts and the constructive feedback from delegates, the conference improves. We are confident that this year’s conference will be the best ever, and I look forward to seeing you there.

2006 International Conference on Compound Semiconductor Manufacturing Technology

2006 CONFERENCE SPONSORS
(partial list, as of January 13, 2006)
MANTECH is an independent not-for-profit organization whose mission is to promote technical discussion and scientific education in the compound semiconductor manufacturing industry. The continued success of the conference is enabled by donations from corporate sponsors. The 2006 MANTECH Conference Committee gratefully acknowledges the support from our sponsors.

CONFERENCE HIGHLIGHTS
MANTECH’s 2006 Technical Program Committee has assembled an excellent program which includes 71 outstanding presentations on a wide variety of topics related to compound semiconductor manufacturing technology. The broad and worldwide scope of our industry is reflected by our mix of contributors. Over 50 industry, government, and university labs are represented. 23 of our papers are international, and several cross national boundaries, with collaborating authors from various countries. In addition, 12 student papers are scheduled, indicating a healthy future for our industry. Also, as is traditional for MANTECH, the strong technical program is augmented by a variety of social events, providing opportunities to network and build professional relationships.

Our week begins on Monday, April 24^th, with our Workshop. Workshop attendees may select from a total of 8 sessions, which will be running two in parallel. In one, an opening reliability tutorial will be followed by a series of three workshops on manufacturing topics: WIP management, experimental design, and six-sigma lean manufacturing. In the other, a pair of morning treatments of processing topics: tutorials on resist and polymer removal and on epi growth, will be followed by two WBG-related workshops: GaN processing and Wide Bandgap (WBG) commercial applications.

The Industry Exhibits feature many prominent suppliers to the compound semiconductor industry. The exhibits open on Monday evening with the first MANTECH social event, the Exhibits Reception. The exhibits continue throughout Tuesday, when attendees may enjoy breakfast, morning and afternoon breaks, and the Exhibits Lunch while browsing the exhibit aisles. A new and popular event from last year will be repeated: the Exhibitors’ Forum will be held immediately following the Exhibits Lunch on Tuesday.

The technical sessions begin Tuesday morning, April 25^th, with the Plenary Session, which features three invited presentations that take a high-level look at our industry. Opening the session will be Oded Tal of MAX/IEG who will present the results of a comparative study of the operational levels of representative fabs in our industry. Factors such as capacity, cost, cycle time, and yield are discussed. It is hoped that this benchmarking study will help foster operational excellence within the CS industry, giving us a technical and competitive edge. The second talk, by John Zingaro of Northrop Grumman, takes a look at one of our key markets, military technology. It was this market which served to “jump start” our industry initially and it remains a key factor in pushing the leading edge. What are the current and future applications/requirements that might be addressed by CS technology? This talk will discuss these questions. Rounding out our Plenary Session is a presentation by Robert Walker of YEBY Associates on a subject that should be of great interest to all CS technologists: China’s semiconductor industry and how it will impact our futures. We’ve all read of the booming growth in China in recent years. Dr. Walker will provide us with details and a discussion of where it is leading.

Following the Plenary Session, the general Technical Sessions, presented in parallel sessions Wednesday and Thursday, feature papers presented by leading technologists addressing key areas of compound semiconductor technology: Manufacturing, HBTs, FETs, HEMTs, Wide Bandgap Technology, Processing, Materials, Reliability, Test, and Optoelectronics.

Of special note among the Technical Sessions, Tuesday afternoon’s Worldwide GaN Session includes presentations from three government programs focused on GaN development in the USA, Japan, and the European Union. The session is rounded out by an invited presentation from Toyota on GaN automotive applications. Is GaN the future? Agree or disagree but come and listen.

MANTECH social events continue on Tuesday evening with the International Reception. Attendees will take the Skyride to the Peak Chalet at the top of Grouse Mountain, where we’ll enjoy drinks, west coast cuisine and spectacular views of Vancouver and the Pacific Ocean 3,700 feet below.

Wednesday afternoon this year features a revival of the MANTECH Panel Session. An important topic (our future in the cell phone industry) will be discussed by a panel of experts. This will be followed by the popular Rump Sessions, complemented with snacks and drinks. Attendees may join any of the three parallel topics, where moderators will encourage informal, highly interactive, lively and informative discussions.

Traditionally one of the highlights of the conference, the Interactive Forum will be held on Thursday, along with a Lunch Reception. This is a poster session that includes papers that could not be fitted into the other technical sessions, as well as all of the presented papers. It provides an excellent opportunity to meet with all the authors and to discuss the papers casually over lunch. A Best Poster Award will be given based on a vote of attendees.

The conference ends with our Conference Closing Reception, which follows immediately after the Interactive Forum. At this time a raffle drawing will be held for a prize to be announced. All those who complete and submit their Feedback Forms will be entered. In addition, the Best Poster Award will be given, based on a vote of the attendees. And it will be a last chance to exchange business cards, discuss issues of mutual interest, and say good-bye until next year.

WORKSHOPS
Each year CS MANTECH provides many opportunities for sharing technical knowledge and learning from one another in an interactive environment. Be sure to take advantage of your first chance to do so by attending the workshops this year. The sessions will be presented on Monday April 24^th, by industry experts with a wealth of knowledge and hands-on experience. Parallel sessions will be offered, covering a wide range of topics including compound semiconductor reliability, manufacturing, processing, and wide bandgap technologies. The workshop schedule can be found in this pamphlet at the beginning of the technical program listing (page 17).

The first session will lead off with “Reliability – Beyond the Basics”. Bill Roesch of TriQuint Semiconductor will briefly review reported history and basic concepts and then launch into emerging topics on reliability. Some of the ideas Bill will discuss are: 1) The Ponce De Leon Syndrome - why reliability engineers should give up the quest for immortality; 2) Everybody Loves Random - are “chance” failures for real? 3) Failure Analysis - the CSI of semiconductors; 4) Big Customers Rule – how the “K Factor” brings together volume, quality, and reliability concepts; and 5) Defect Amplification – finding the shape of your Bathtub Curve. Although the topics extend beyond traditional reliability theories, Bill has targeted his discussion towards process/manufacturing engineers at all levels.

Following reliability, there will be three manufacturing workshops. First, “WIP Management and Cycle Time Reduction” will be presented by Professor Rob Leachman from the University of California at Berkeley. Professor Leachman will discuss methods to effectively manage WIP and reduce cycle times in compound semiconductor fabs. To demonstrate where the CS community may be able to improve, actual case studies from Silicon fabs will be provided. Effective approaches to two broad aspects of cycle time reduction will be highlighted. First, methodology to calculate entitlement cycle times will be introduced. This enables management and engineers to quantify the cycle time delta from any proposed engineering change. They can thereby develop process technology, install equipment sets and plan qualifications making the fab capable of good cycle time performance. Second, techniques for WIP management and scheduling are explained that close the gap between execution and entitlement, enabling CS fabs to achieve the cycle time performance of which their equipment and process are truly capable.

Next, Mario Perez-Wilson from Advanced Systems Consultants will present “Experimental Designs in CS-Fabrication” Typical experiments in CS-Fabrication involve multiple process steps, multiple factors, and multiple levels, as well as multiple experimental units, where the relationship between the factors may be crossed or nested, and the levels may be fixed or random. This leads to very complex experimental designs, which if not designed properly, may lead to incorrect analysis, and erroneous conclusions. This workshop will cover basic factorial designs, and then present these multi-Process-Factor-Level-Experimental Unit mixed-effect models. Applications of the models will be shown using examples from Chemical Mechanical Planarization (CMP) and SiGe Epitaxial Deposition.

“Six Sigma-Lean: Impacting the Top and Bottom Line” by Dana Crowe of M/A COM Tyco Electronics will conclude this session. This workshop will provide an understanding of how Six Sigma and Lean have been applied to drive top line growth and how they impact the bottom line. Using case studies and applications, the practical side of implementing the tools and process of Six Sigma-Lean in design, operations, and the transactional side of business will be explored.

In parallel with the above workshops, Processing and WBG workshops will be presented:

To start the processing session, “Practical Applications in Resist and Polymer Removal”, will be presented by John Moore of DAETEC. This workshop will begin with a background of resist types, organic dielectrics, and adhesives. Details of how to match chemistries, and how to model the systems will then be provided. In addition, applications will be presented, such as simple stripping, post-etch residue removal, lift-off, re-work, and demounting thinned substrates. Mr. Moore will also offer suggestions on process design and tooling.

Next Yohei Otoki from Hitachi will present an “Epi Growth Tutorial”. This workshop will provide an overview of epitaxial growth methods, mainly focused on III-V semiconductor materials for microwave devices, MESFETs, HEMTs and HBTs. It will include the history of these technologies, the current business situation, and technical descriptions of how each method works. In addition, the pros and cons of MBE vs. MOCVD will be discussed as applied to different material systems. Recent topics for GaN-HEMT epi-growth will also be reported.

As a transition between processing and WBG topics, G. David Via from AFRL will present “AlGaN/GaN HEMT Processing” This workshop will provide an introduction to AlGaN/GaN HEMT processing using GaAs processing as a reference. Critical front end steps (isolation, ohmic contacts, schottky contacts and passivation) will be discussed in detail with an emphasis on how GaN processing requirements differ from GaAs processing. Device results will be used to show the impact of these differences. Mr. Via will conclude with a general discussion of state-of-the-art GaN results and outstanding technical challenges.

To close out the session, Stuart Hodge of Cree, Inc. will discuss “Wide Bandgap Commercial Applications”. After many years of research, Wide Bandgap materials are now shipping in high volume power applications. In particular, the commercialization of Silicon Carbide Power devices, (Schottky Diodes, MOSFETs, JFETs, and Bipolar devices), are impacting everything from Desktop PC power supplies to Hybrid Electric Vehicle drives. This workshop will explore the present and future role of Wide Bandgap materials in Energy Efficiency.

Please see our website, www.csmantech.org for more information. The Workshop Registration fee covers all workshops. Except for student registration, the Workshop is not included in the Conference Registration Fee.

INDUSTRY EXHIBITS
2005 saw a resurgence in the compound semiconductor industry, a welcome change from the slow recent years. Fabs are full again and capacity and capability expansion is once again in the air. In addition, interest in both silicon carbide and gallium nitride has continued to increase, sustaining equipment and supply demand in those areas. Our equipment and material suppliers provide the infrastructure to make all our production possible. The industry exhibition is an opportunity for these suppliers to showcase the products that will help attendees in their future development and manufacturing efforts.

The 2006 Industry Exhibition begins Monday evening, April 24, after the Technical Workshop, and continues all day Tuesday, April 25. The exhibition is an ideal forum for conference and exhibition attendees to interact in a relaxed environment. This year, there will be three events held in the exhibit area: the Exhibits Reception Monday evening, 6:00 PM - 9:00 PM; a continental breakfast on Tuesday, 7:00 AM – 8:00 AM; and an Exhibits Luncheon on Tuesday, 12:10 PM - 1:30 PM. The exhibits will open formally after the Plenary Session at 10:00 AM, so all may attend the opening session. Throughout Tuesday there will also be several longer coffee breaks. We believe this format is an excellent opportunity to visit with your existing customers or suppliers and to meet new ones.

EXHIBITS RECEPTION
The Exhibits Reception will be held in the Exhibits Area (Vancouver Island Room and B.C. Ballroom) Monday evening, April 24, from 6:00 PM to 9:00 PM. Buffet style finger food will be offered, so instead of worrying about dinner, please stop in when you arrive, meet colleagues and see what our vendors have to offer to help you build successful products.

EXHIBITS LUNCHEON
The Exhibits Luncheon will be held on Tuesday, April 25, from 12:10 PM to 1:30 PM in the Exhibits Area. Please come and have your lunch while you continue your discussions with our compound semiconductor industry vendors and network with colleagues and clients from around the world.

EXHIBITORS’ FORUM
This year sees a repeat and expansion of last year’s successful and popular Exhibitors’ Forum. This will take place on Tuesday April 25 from 1:30 PM to 3:20 PM (immediately after the Exhibits Luncheon). Here exhibitors have the opportunity to present their latest technologies and offerings in an informal and relaxed environment. The detailed schedule for this event will be available at the conference in our “Guide to Exhibits”.

INTERNATIONAL RECEPTION
On Tuesday evening at 6:30pm, buses will take us on 15-minute trip to Grouse Mountain, the “Peak of Vancouver” for the International Reception. Attendees will take the Skyride, North America’s largest aerial tramway system, to the Peak Chalet, constructed of stone and timber. At the chalet, we’ll enjoy drinks, west coast cuisine and spectacular views of Vancouver and the Pacific Ocean 3,700 feet below. This reception provides an excellent opportunity to meet industry colleagues and renew acquaintances in a unique and memorable setting. Visit two grizzly bears in a wildlife refuge a short walk from the Peak Chalet, see a stunning documentary in the Theatre In the Sky, Grouse Mountain’s high-definition cinema, and enjoy live music and conversation in the Peak Chalet before heading back to the hotel at or before 10:00pm.

MANTECH extends an invitation to family and friends that may be accompanying you at the Conference to join us at this special event. Guest tickets are $50 each. We strongly encourage you to purchase guest tickets at the time of your registration to ensure space at the reception.

CONFERENCE CLOSING RECEPTION
A Conference Closing Reception will wind up the 2006 edition of MANTECH, which will follow immediately after the Interactive Forum luncheon. Drinks and snacks will be provided to foster a congenial, final opportunity to exchange business cards, ideas, and experiences.

New this year is a Feedback Form Raffle. Your opinion on the Feedback Form is very valuable to the MANTECH committees in structuring the conference and programs year-to-year and in choosing the best paper awards. This year when you turn in your Feedback Form, you enter a raffle. Prize to be announced. It’s as simple as that. The drawing will be held at the Conference Closing Reception. In addition, votes will be tallied and the Best Poster Award winner announced.

At the time of this Advance Program preparation, a number of other exciting possibilities are being evaluated by the MANTECH committees for the Conference Closing Reception. Check our website for details!

2005 BEST PAPER AWARDS
CS MANTECH tradition is to formally recognize the authors of the best paper and best student paper of the previous conference, as determined from the conference attendee votes tallied from your feedback forms. These awards will be presented during the conference introductions on Tuesday, April 25^th.

The authors of the Best Paper receive the He Bong Kim award, named in honor of Dr. He Bong Kim, the founder of the International Conference on Compound Semiconductor MANufacturing TECHnology. The He Bong Kim award winner for the 2005 Conference is William J. Roesch of TriQuint Semiconductor Inc., for his invited paper ‘Outstanding Issues in Compound Semiconductor Reliability’.

The Best Student Paper for the 2005 Conference ‘Investigation of Contact Metal Stacks for Submicron GaN HEMT’, was authored by Y. Knafo, I. Toledo, I. Hallakoun, J. Kaplun, G. Bunin, T. Baksht, B. Hadad, and Y. Shapira, from the Tel-Aviv University, and Gal-El (MMIC). The principal student author Y. Knafo will receive a special cash award of $1000.

SEMI STANDARDS MEETING
The SEMI Standards meeting is scheduled for Wednesday, April 26, from 5:30 PM to 7:30 PM (immediately following the Rump Sessions). The SEMI Compound Semiconductor (GaAs, InP and SiC) Committee invites MANTECH Conference attendees interested in the development of internationally approved standards for Wafer Specifications to attend this meeting. Topics being addressed are GaAs, InP, and SiC dimensions/orientations and electrical properties, Epitaxial Layer Specifications (which properties should be specified, and how they are to be verified), and Non-Destructive Test Methods. Based in San Jose, CA, SEMI is an international trade association serving more than 2,400 companies participating in the semiconductor and flat panel display equipment and materials markets. SEMI maintains offices in Brussels, Moscow, Tokyo, Seoul, Hsinchu, Beijing, Singapore, Austin, Boston and Washington, DC. For additional information, please contact: Co-Chair: James Oliver of Northrop Grumman at 410-765-0117 or j.oliver@ngc.com, Co-Chair: Russ Kremer of Freiberger Compound Materials at 937-291-2899 or russ@fcm-us.com, or SEMI Standards Engineer Ian McLeod at 408-943-6996 or imcleod@semi.org.

Registration and Local Arrangements Chair
Mary Young, Integrity Semiconductor

Executive Advisory Board
Jim Sewell, Air Force Research Laboratory
Chun-Lim Lau, Booz Allen Hamilton
Bob Surridge, Gain Microwave Corporation

MANTECH Support
Lynn Fincher, Webmaster
Margaret Doyle, Executive Assistant

Jon Abrokwah, Freescale Semiconductor
Kamal Alavi, Raytheon RF Components
John Almerico, Tegal Corporation
Hani Badawi, AXT, Inc.
Zaher Bardai, Raytheon
Doug Barlage, North Carolina State University
John Blevins, Air Force Research Laboratory
Karlheinz Bock, Fraunhofer Institute
Karim Boutros, Rockwell Scientific
Doug Carlson, M/A-COM
P. C. Chao, BAE Systems
Paul Cooke, EMCORE Corporation
Jim Crites, M/A-COM
Dieter Eissler, OSRAM Opto Semiconductor GmbH
Peter Ersland, M/A-COM
Patrick Fowler, Anadigics, Inc.
Mike Fresina, RF Micro Devices
Remis Gaska, Sensor Electronic Technology
Drew Hanser, Kyma Technologies, Inc.
Allen Hanson, Nitronex Corporation
Dick Hockett, Evans Analytical Group
Yung-Chung Kao, IntelliEPI
Tamotsu Kimura, OKI Optical Components
Judy Kronwasser, NOVASiC
Steve Mahon, TriQuint Semiconductor
John Martinez, Sandia National Laboratories
Miro Micovic, HRL
Alan Mills, III-Vs Review
Eizo Mitani, Eudyna Devices USA, Inc.
Yorito Ota, Matsushita Electric Industrial Co., Ltd.
Noren Pan, Microlink Devices
Tim Phillips, QinetiQ, Ltd.
Karen Renaldo, Northrop Grumman ES
Tom Ryan, Accent Optical Technologies
Rob Sadler, Northrop Grumman ES
Keith Salzman, TriQuint Semiconductor Texas
Shyh-Chiang Shen, Georgia Tech
Andy Souzis, II-VI, Inc.
Mike Sun, Skyworks Solutions, Inc.
Oded Tal, MAX International Engineering Group
Zhuang Tang, WJ Communications, Inc.
Julien Thuret, Picogiga
Der-Wei Tu, Win Seminconductor
John Varesi, U.S. Army Night Vision Laboratory
Dave Via, Air Force Research Laboratory
David Wang, Global Communication Semiconductors
Roger Welser, Kopin Corporation
Russ Westerman, Unaxis
Dennis Williams, Fairchild Semiconductor

Monday, April 24

WORKSHOP
Chair: Heather Knoedler, Skyworks Solutions, Inc.
On-site Coordinator: Scott Sheppard, Cree, Inc.

8:00 AM

Welcome/Introductions

8:15 AM

Reliability – Beyond the Basics
Bill Roesch, TriQuint Semiconductor

8:15 AM

Practical Applications in Resist and Polymer Removal
John Moore, DAETEC, Inc.

10:00 AM

BREAK

10:15 AM

WIP Management
Professor Rob Leachman, UC Berkeley

10:15 AM

Epitaxial Growth Tutorial
Yohei Otoki, Hitachi Cable Ltd

12:00 PM

WORKSHOP LUNCH

1:15 PM

Experimental Designs in CS-Fabrication
Mario Perez-Wilson, Advanced Systems Consultants

1:15 PM

AlGaN/GaN HEMT Processing
G. David Via, Air Force Research Laboratory

3:00 PM

BREAK

3:15 PM

Six Sigma-Lean: Impacting the Top and Bottom Line
Dana Crowe, M/A-COM, Inc.

3:15 PM

Wide Bandgap Commercial Applications
Stuart Hodge, Cree, Inc.

5:00 PM

WORKSHOP CLOSE

6:00 PM

EXHIBITS RECEPTION

Tuesday, April 25

8:00 AM

Welcoming Ceremonies
Deb Green
Conference Chair

8:10 AM

Conference Awards
Bob Surridge, Gain Microwave Corp.
Executive Advisor, Past Conference Chair

8:20 AM

Technical Program Highlights
George Henry, Northrop Grumman ES
Technical Program Chair

SESSION 1: PLENARY

Chair:

George Henry, Northrop Grumman ES

8:30 AM

Invited Presentation
Compound Semiconductor Benchmark Study
Oded Tal, Ariel Meyuhas, MAX International Engineering Group

9:00 AM

Invited Presentation
Future Trends for Microwave Compound
Semiconductors in Military Systems
John Zingaro, Northrop Grumman ES

9:30 AM

Invited Presentation
China’s Semiconductor Industry: The Impact on Global Manufacturing
Robert Walker, YEBY Associates, LLC

10:00 AM

BREAK

SESSION 2: MANUFACTURING

Chair:

P. C. Chao, BAE Systems

10:30 AM

Semiconductor Innovation and Integration for Next-Generation 3G Multimedia Devices
Brian Daly, Skyworks Solutions, Inc.

10:50 AM

Release for Production of a 150 GHz, 125nm Gate In_0.4 Metamorphic GaAs HEMT MMIC Process
J. Bellaiche, P. Baudet, S. Demichel, M. Renvoise, H. Maher, J. F. Pautrat, OMMIC

11:10 AM

The First 0.1mm 6” GaAs PHEMT MMIC Process
L. Gunter, D. Dugas, S. Yang, P. Seekell, M. Gerlach, J. Diaz, J. Lombardi, P.C. Chao, K. Nichols, W. Kong, B. Golja and K.H.G. Duh, BAE Systems

11:30 AM

The Manufacture of Optical Components on 4-inch InP in a GaAs Production Fab
E. Beam, T. Chou, J. Jimenez, A. Ketterson, A. MacInnes, A. Mahajan, P. Saunier, D. Wohlert, C. Youtsey, TriQuint Semiconductor

11:50 AM

The Effective Use of Process Control Plans and Process Failure Mode Effects Analysis in a GaAs Semiconductor Manufacturing Environment
Daniel J. Le Saux, Skyworks Solutions, Inc.

12:10 PM

EXHIBITS LUNCHEON

Chair:

Exhibitors’ Forum
Marty Brophy, TriQuint Semiconductor

SESSION 3: WORLDWIDE GaN

Chair:

Karim Boutros, Rockwell Scientific

3:30 PM

Invited Presentation
Wide-Bandgap Semiconductor Devices for Automobile Applications
H. Ueda, M. Sugimoto, T. Uesugi, and T. Kachi, Toyota Central R&D Labs, Inc

4:00 PM

Invited Presentation
Preliminary Results from Phase II of the Wide Bandgap Semiconductor for RF Applications (WBGS-RF) Program
Mark Rosker¹, Harry Dietrich², Alfred Hung³, Chris Bozada⁴, ¹Defense Advanced Research Projects Agency / Microsystems Technology Office , ²Office of Naval Research, ³Army Research Laboratory, ⁴Air Force Research Laboratory

Invited Presentation
Development of AlGaN/GaN High Power and High Frequency HFETs under NEDO's Japanese National Project
Yasushi Nanishi, Ritsumeikan University

5:00 PM

KORRIGAN: Development of GaN HEMT Technology in Europe
G. Gauthier¹, Francois Reptin², ¹Thales Airborne Systems, ²DGA

7:00 PM

INTERNATIONAL RECEPTION
(buses start leaving at 6:30 PM)

Wednesday, April 26

SESSION 4: MATERIALS

Chair:

Hani Badawi, AXT, Inc.

8:00 AM

Invited Presentation
The SEMI International Standards Program – History, Successes and Lessons Learned to Address Compound Semiconductor Manufacturing Challenges
Bettina Weiss, SEMI

8:30 AM

White Light Interferometry – A Production Worthy Technique for Measuring Surface Roughness on Semiconductor Wafers
Roy T. Blunt, IQE (Europe) Ltd.

8:50 AM

Overcoming Difficulties in Photoreflectance Measurement of Product HBTs,
E.M. Rehder, P. Rice, K.S. Stevens. C. R. Lutz, Kopin Corp.

9:10 AM

An Overview of Gallium Nitride Substrate Materials Developments for Optoelectronic and Microelectronic Applications
Drew Hanser¹, L. Liu¹, E. Preble¹, D. Tsvetkov¹, M. Tutor¹, M. Williams¹, K. Evans¹, Y. Zhou², D. Wang², C. Ahyi², C. Tin², J. Williams², M. Park², D. Storm³, D. Katzer³, S. Binari³, ¹Kyma Technologies, Inc., ²Auburn University, ³Naval Research Lab

9:30 AM

Recent Achievement of the SopSiC Substrates for High Power and High Frequency Applications
P. Bove¹, H. Lahreche¹, R. Langer¹, D. Da Cruz¹, B. Faure², F. Letertre², ¹Picogiga International, ²Soitec

SESSION 5: RELIABILITY & TEST

Chair:

Peter Ersland, M/A-COM, Inc

8:00 AM

Invited Presentation
Perfect Quality for Free?!
Nien-Tsu Shen, Skyworks Solutions, Inc.

8:30 AM

Statistical Quality Control of Wafer Level DC Die Sort Test
Y. Z. Wang, R. S. Persaud, R. C. Salvador and D. J. Troy, Anadigics, Inc.Y. Z. Wang, R. S. Persaud, R. C. Salvador and D. J. Troy, Anadigics, Inc.

8:50 AM

SiN Capacitors and ESD
Gergana I. Drandova, John M. Beall, Kenneth D. Decker, TriQuint Semiconductor

9:10 AM

The Reliability Study of MIM Capacitor Built On Top of Backside Via In III-V Compound MMIC
X. Zeng, M. Barsky, J. Uyeda, D. Farkas, F. Yamada, M. Biendenbender, D. Eng, J. Wang, R. Lai, Northrop Grumman ST

9:30 AM

Lifetime of SiN Capacitors Determined from Ramp-Voltage and Constant-Voltage Testing
H. C. Cramer, J. D. Oliver, R. J. Porter, Northrop Grumman ES

9:50 AM

BREAK

SESSION 6: PROCESS 1 – THIN FILMS & DRY ETCH

Chair:

Steve Mahon, TriQuint Semiconductor

10:20 AM

3.3fF/um² 40V BST MIM Capacitor Suitable for Above MMIC Integration
Satoshi Horiuchi, K. Matsumoto, M. Sakachi, T. Ooki, H. Nakamura, K. Adachi, M. Shinohara, Sony Corp.

10:40 AM

High Value Thin Film Resistor for GaAs IC Manufacturing
Fabian Radulescu¹, Jinhong Yang¹, Paul Miller¹, Ron Herring¹, Chi-Fung Lo², Wolfgang Liebl³, ¹TriQuint Semiconductor, ²Praxair Surface Technology-MRC, ³Infineon Technologies AG

11:00 AM

Student Presentation
Comparison of Different GaN Etching Techniques
Flei Ma, K. Fareen Adeni, Chang Zeng, Yawei Jin, Doug Barlage, North Carolina State University

11:20 AM

Bias Annealing Behavior of Plasma-Induced Defects in n-GaN Exposed to Plasma
S. Nakamura, M. Suda, M. Suhara, and T. Okumura, Tokyo Metropolitan University

SESSION 7: OPTICAL & NOVEL DEVICES

Chair:

Jon Abrokwah, Freescale Semiconductor

10:10 AM

Invited Presentation
Status and Progress in InP Optoelectronic Processing: Towards Higher Levels of Integration
Richard P. Schneider, Jr., et al, Infinera Corp.

10:40 AM

Compound Semiconductor MOSFET With High-k Dielectric
Karthik Rajagopalan, Ravi Droopad, Jon Abrokwah, and Matthias Passlack, Freescale Semiconductor

11:00 AM

A Flip-chip Low Band Harmonic Filter Based on GaAs Integrated Passives
Jon Abrokwah, Sergio Pacheco, Gilles Montoriol, Li Li, Robert Bettiga, Philip Bowles, Freescale Semiconductor

11:20 AM

Student Presentation
27 GHz Flip-Chip Assembled PHEMT Oscillator
Yue-ming Hsin, Yu-An Liu and Che-ming Wang, Taiwan National Central University

11:40 AM

LUNCH (Attendees Choice)

SESSION 8: PROCESS II: COST-REDUCED PROCESSING

Chair:

Pat Fowler, Anadigics, Inc.

1:10 PM

Reduction of Chlorinated Solvents in GaAs Manufacturing
Victoria Williams, Harold Isom, Thomas Nagle, Cary Sellers, Sean Hillyard, Samuel Roadman, Sumir Varma, TriQuint Semiconductor

1:30 PM

Reduction of Platinum Metal Usage in GaAs IC Metallization
L. Luu-Henderson, L. Rushing and S. Tiku, Skyworks Solutions, Inc.

1:50 PM

Significant Step in Wafer Yield Optimization and Operation Cost Reduction Due to Dicing Innovation
Mark Mueller, Rene Hendriks, Peter Chall, ALSI International

2:10 PM

Damage-Free Dicing of SiC Wafers by Wafer-Jet-Guided Laser
Tom Levesque¹, Delphine Perrottet², Bernold Richerzhagen², ¹Synova-USA, ²Synova-SA

SESSION 9: HBT

Chair:

Noren Pan, Microlink Devices

1:10 PM

A High Yield Manufacturable BiFET Epitaxial Profile for High Volume Production
Mike Sun¹, Pete Zampardi¹, J. Li¹, R. Ramanathan¹, A.G. Metzger¹, C. Cismaru¹, Vincent Ho¹, L Rushing¹, K S. Stevens², M. Chaplin², R. E. Welser², ¹Skyworks Solutions, Inc., ²Kopin, Corp.

1:30 PM

InGaP-Plus: A Low Cost Manufactureable GaAs BiFET Process Technology
Mohsen Shokrani, Kezhou Xie, Boris Gedzberg, Wojciech Krystek, Prabhu Mushini, Aditya Gupta, Pat Fowler, William Peatman, Anadigics, Inc.

1:50 PM

Student Presentation
High Performance Metamorphic InP/GaAsSb/InP "Type-II" DHBTs Grown on GaAs Substrates
Y.Zeng¹, H. Liu¹, N. Tao¹, C. Bolognesi¹, M. Chen², W. Zhou², J. Zhu², Y. Cai², W. Tang², K. Chen², K. Lau², ¹Simon Fraser University, ²Hong-Kong University of Science and Technology

2:10 PM

Student Presentation
Investigation of Base-Collector Parasitics for Multifinger Emitter and Base Geometries in GaAsSb/InP Type-II DHBTs
¹B. Chu-Kung, ²S. Shen, ¹W. Snodgrass, and ¹M. Feng, ¹University of Illinois Department of ECE, ²Georgia Institute of Technology

SESSION 10: PANEL SESSION

Chair:

Mike Barsky, Northrop Grumman ST

2:40 PM – 3:40 PM

Is there a future role for compound
semiconductors in consumer
communications? Will it all be Si?

SESSION 11: RUMP SESSIONS

Chair:

Keith Salzman, TriQuint Semiconductor

3:50 PM – 4:50 PM

1.	Focus on Fab Operations Management to Reduce Cost. Moderator: Steve Mahon, TriQuint Semiconductor
2.	What is the Best Substrate for GaN Devices? Moderator: Drew Hanser, Kyma Technologies, Inc.
3.	Flexible Manufacturing, eg, R&D and Manufacturing in the Same Facility Moderator: Oded Tal, MAX International Engineering Group

Thursday, April 27

SESSION 12: HIGH VOLTAGE FETs

Chair:

Miro Micovic, HRL

8:00 AM

Invited Presentation
Recent Progress of Highly Reliable GaN-HEMT for Wireless Base Station
Toshihide Kikkawa, Kenji Imanishi, Mashhito Kanamura, Kazukiyo Joshin, Fujitsu Laboratories Ltd.

8:30 AM

High-Efficiency Amplifiers with Advanced GaN/AlGaN HEMTs on SiC
Scott Sheppard, Bill Pribble, R. Peter Smith, Adam Saxler, Scott Allen, Jim Milligan, and Ray Pengelly, Cree, Inc.

8:50 AM

Infrared and Raman Temperature Measurements in AlGaN/GaN-based HFETs
A. Sarua¹, Hangfeng Ji¹, M. Kuball¹, M.J. Uren², T. Martin², K. P. Hilton², R. S. Balmer², ¹University of Bristol, ²QinetiQ, Ltd

9:10 AM

Mass-Production of High-Voltage GaAs and GaN Devices
E. Mitani, H. Haematsu, S. Yokogawa, J. Nikaido, and Y. Tateno, Eudyna Devices, Inc.

9:30 AM

An Ion-Implanted GaAs MESFET Process for 28V S-Band MMIC Applications
M.J. Drinkwine, T. Winslow, D. Miller, D. Conway, B. Raymond, M/A-COM, Inc.

SESSION 13: PROCESS III – BACKSIDE

Chair:

Russ Westerman, Unaxis

8:10 AM

Reversible Wafer Bonding; Challenges in Ramping up 150mm GaAs Wafer Production to Meet Growing Demand
Suzanne Combe, John Cullen, Filtronics ICS

8:30 AM

Defect Reduction in Through Wafer Via Photolithography Processing
J. Riege, T. Nguyen, H. Knoedler, B. Darley, Rick Clark, N. Ebrahimi, S. Mony, S. Tiku, Skyworks Solutions, Inc

8:50 AM

The Effects of Processing a Negative Chemically Amplified (CAMP) Resist on Micromasking During InP Backside Via Etch
T.L. Brown, M. Farhoud, T. Engel, B. Keppeler, E. Ehlers, R. Miller, M.W. Dvorak, M. Bonse, T.S. Low, K. Seaward, D. Dutton and D.C. D’Avanzo, Agilent Technologies

9:10 AM

Substrate Via Etch Profile Optimization Using RIE and Wet Etch Processes
S. E. Roadman, C. Youtsey, C. Sellers, and H. Isom, TriQuint Semiconductor

9:30 AM

Development of Backside Process for Use with Solder Paste Die Attach
Jason Fender and Terry Daly, Freescale Semiconductor

9:50 AM

BREAK

SESSION 14: WIDE BANDGAP

Chair:

Shyh-Chiang Shen, Georgia Tech

10:10 AM

Invited Presentation
Status of SiC Power Devices and Manufacturing Issues
Anant Agarwal and Sei-Hyung Ryu, Cree, Inc.

10:40 AM

High-Yield Silicon Carbide Vertical Junction Field Effect Transistor Manufacturing for RF and Power Applications
Victor Veliadis, Li-Shu Chen, Megan McCoy, Ty McNutt, Eric Stewart, Robert Sadler, Alfred Morse, Steve Van Campen, Chris Clarke, Gregory DeSalvo, Northrop Grumman ES

11:00 AM

Technology Development of 4H-SiC RF BJTs with 5GHz F_max Bart Van Zeghbroeck^1,2, Ivan Perez², Feng Zhao^1,2 and John Torvik², ¹University of Colorado, ²Advanced Power Technology

11:20 AM

AlGaN/GaN MIS HEMT with AlN Dielectric|Chen Tangsheng, Jiao Gang, Li Zhonghui, Li Fuxiao, Shao Kai, Yang Naibin, Nanjing Electronic Devices Institute

11:40 AM

SiC, Sapphire, and GaN Materials Status into Opto and RF Businesses
Philippe Roussel, Yole Developpement

SESSION 15: HIGH SPEED TECHNOLOGIES

Chair:

Roger Welser, Kopin Corp.

10:20 AM

Low Power High Speed Circuits with InAs-based HBT Technology
C. Monier, A. Cavus, R. Sandhu, A. Oshiro, D. Li, D. Matheson, B. Chan, P. Nam, and A. Gutierrez-Aitken, Northrop Grumman ST

10:40 AM

An Ultra-Low Power InAs/AlSb HEMT X-Band Low-Noise Amplifier and RF Switch
Jonathan Hacker¹, Joshua Bergman¹, Gabor Nagy¹, Gerard Sullivan¹, C. Kadow², H.-K. Lin², A. C. Gossard², Mark Rodwell², B. Brar¹, ¹Rockwell Scientific, ²UC Santa Barbara

11:00 AM

Student Presentation
MOCVD Grown Metamorphic InAlAs/InGaAs HEMTs on GaAs Substrates
Chak-wah Tang, Jiang Li, Kei May Lau, Kevin J. Chen, Hong Kong University of Science and Technology

11:20 AM

Student Presentation
Temperature Dependence of InGaP/InGaAs/GaAs pHEMTs
Man Ni¹, P. Fay¹, N. Pan²,¹University of Notre Dame, ²Microlink Devices

11:40 AM

Beyond CMOS : Logic Suitability of In_0.7Ga_0.3As HEMT
D.-H. Kim and J. A. del Alamo, Massachusetts Institute of Technology (MIT)

12:10 PM - 2:10 PM

LUNCH RECEPTION &

SESSION 16: INTERACTIVE FORUM

Chairs:

Karen Renaldo, Northrop Grumman ES
Judy Kronwasser, NOVASIC

16.1

Visual and Electric Effects of Ohmic Metal Erosion from Later Process Steps
Thorsten Saeger, Martin J. Brophy, Fabian Radulescu, Tertius Rivers, Corey Jordan, Dorothy Hamada, TriQuint Semiconductor

16.2

Student Presentation
InP/InGaAs DHBT Large Signal Model for Nonlinearity Harmonic Predictions in ICs
Yu-Ju Chuang¹, J. W. Lai¹, Kurt Cimino¹, Milton Feng¹, Minh Le², Raymond Milano², R.. B. Elder³, Frank Strolli³, ¹Dept of ECE Univ of Illinois, ²Vitesse Semiconductor, ³BAE Systems

16.3

SEMI Standardization Efforts in Compound Semiconductors,
James D. Oliver¹ and Russ Kremer², ¹Northrop Grumman ES, ²Freiberger USA

16.4

A Chemical and Thermal Resistant Wafer Bonding Adhesive Simplifying Wafer Backside Processing
A. Smith¹, J. Moore², and B. Hosse³, Brewer Science, Inc., ²DAETEC, Inc., ³RF Micro Devices

16.5

Student Presentation
Improvements in the Process for Electrodeposition of Au-Sn Alloys
Nasim Morawej and Douglas G. Ivey, University of Alberta

6.6

Defect Formation in GaN Introduced During Plasma Processing
S. Nakamura, M. Suda, M. Suhara, and T. Okumura, Tokyo Metropolitan University

16.7

Determining Inductor Interactions with a Design of Experiment
Michael Meeder, Michael Fresina, Denny Limanto, Marc Schulze Tenberge, RF Micro Devices

16.8

Student Presentation
Manufacture of Mesa-Type and Air-Bridge Gate In_0.5Al_0.5As/In_0.5Ga_0.5As Metamorphic High Electron Mobility Transistors (MHEMTs) with In_xAl_1-xAs Graded Buffer Layers
M. K. Hsu¹, H. R. Chen², W. T. Chen¹, G. H. Chen¹, C. C. Su², and W. S. Lour¹, ¹National Taiwan Ocean University, ²National University of Kaohsiung

16.9

Student Presentation
Optimizing InGaP/GaAs HBT Technology for Distributed Amplifier Applications
Aroonchat Chatchaikarn¹, Wing Yau², Yuefei Yang², and G. P. Li², ¹UC Irvine, ²GCS, Inc.

16.10

Highly Reliable GaAs Planar Airbridged Schottky Diodes for Flight Qualified Millimeter-wave Circuits
Hooman Kazemi and Lan Tran, Rockwell Scientific

16.11

Ensuring High Yield and Good Reliability for Mass-Produced High-Performance Hall Effect Sensors
V. Mosser¹, A. Kerlain¹, R. Morton², Martin J. Brophy², ¹Itron, Inc., ²TriQuint Semiconductor

16.12

Student Presentation
Photonic Crystal Structure Effect on the Enhancement in the External Quantum Efficiency of a Red LED
Taesung Kim^1,2, Aaron J. Danner¹, Paul Leisher¹, Kent D. Choquette¹, Ralph Wirth³, Klaus Streubel³, ¹University of Illinois, ²Natetron Tech., Inc., ³OSRAM Semiconductor GmbH

16.13

Student Presentation
Power 0.15-μm Self-aligned T-Gate PHEMT
B. Hadad², G. Bunin¹, J. Kaplun¹, M. Leibovitch¹, Y. Shapira², ¹Gal-El (MMIC), ²Ben-Gurion University

2:10 PM

CONFERENCE CLOSING RECEPTION
Best Poster Award Presentation
Feedback Form Raffle Drawing

2:50 PM

END OF CONFERENCE

Have a safe trip. See you next year!

TECHNICAL SESSIONS

SESSION 1: PLENARY

Chair:

George Henry, Northrop Grumman ES

Speakers at this year’s plenary session will kick-off the conference with presentations taking a global, high-level look at topics important to our industry.

How close is the operational level of compound semiconductor fabs to that of Si operations? How does your fab compare to the norm for your segment of the industry? Where do we need to focus our primary efforts to achieve operational excellence and competitiveness? In our opening presentation, Oded Tal of MAX/IEG presents the results of a comparative study of operational levels within our industry and will provide some answers to these questions. Our second presentation takes a look at one of our key markets, military technology. Historically, it has been willing to pay a premium for performance in devices and packaging and has been in the forefront directing development of leading edge compound semiconductor technologies. What are the advanced requirements now and what role will compound semiconductors of the future play? John Zingaro of Northrop Grumman will discuss these and other topics. The booming growth of China’s economy is a factor of increasing importance for our industry. What are the implications of these developments on the existing CS industry? New competitors? New markets? Will it follow the model of the “Asian Tigers?” Robert Walker of YEBY Associates takes a look at these issues from a primarily solid state lighting perspective and gives us his informed views.

SESSION 2: MANUFACTURING

Chair:

P. C. Chao, BAE Systems

Following the tradition of this manufacturing technology conference, we have lined up an array of excellent manufacturing papers for you. The session starts with a highly rated paper by Brian Daly of Skyworks Solutions on the trend of innovation and integration of semiconductor devices for the emerging 3G, WiFi and WiMAX market. For those who work in the commercial wireless area, you do not want to miss it. This is followed by a 125nm 40% In MHEMT MMIC paper from OMMIC, detailing the production transfer experience of the developed MHEMT manufacturing process. A 3-stage LNA with an impressive 1.2dB noise figure has been demonstrated with this technology. Liberty Gunter of BAE Systems in Nashua, NH will present her work of world’s first 0.1mm power PHEMT MMIC process on 2mil thick 6” wafers. State-of-the-art K_a-band PHEMT MMICs with 8.3W output power have been demonstrated with this novel process. This demonstrated 6” process is a significant milestone since it makes possible the availability of very high performance PHEMT MMICs at a low cost. But this is not all, we also have a paper from E. Beam of TriQuint sharing his valuable experience in volume production of optical components, such as DFB lasers, PIN and photodiodes, on 4” InP wafers in a GaAs production line. Lastly, Daniel J. Le Saux of Skyworks Solutions describes the technique of using process control plans coupled with a process failure mode effects analysis for timely resolution of manufacturing issues to achieve cost savings in the production line. So sit back and enjoy the presentations.

SESSION 3: WORLDWIDE GaN

Chair:

Karim Boutros, Rockwell Scientific

Wide-bandgap Electronics are certainly getting worldwide attention! This session is composed of four outstanding presentations (three invited) covering the latest on WBG development in Japan, the USA, and Europe. From Japan, Dr. Ueda from Toyota will present an overview on WBG devices for automotive applications. Next, from the United States, we will get a report on the status of the WBG Semiconductor Technology Initiative program sponsored by DARPA’s Microsystems Technology Office. The program is in its second phase, and is aimed at establishing a number of US-based fabrication facilities for WBG materials, devices, MMICs, and T/R modules. We will learn about the latest progress from Dr. Mark Rosker of DARPA/MTO. This will be followed by a discussion of WBG development under NEDO’s Japanese National Project from Prof. Nanishi of Ritsumeikan University. In Europe, a multi-national initiative named KORRIGAN has been formed to develop a stand-alone European supply chain and capability for GaN HEMT technology. A perspective on the consortium will be presented by Dr. Gauthier from Thales.

SESSION 4: MATERIALS

Chair:

Hani Badawi, AXT, Inc.

This session consists of one invited and four contributed papers. The invited paper will be presented by Bettina Weiss, SEMI, in which she will describe the evolution in the SEMI standards in the Si arena and how the CS industry can benefit from seriously adopting a similar path. The first regular paper from IQE (Europe) addresses the use of white light interferometry for measuring surface roughness on semiconductor wafers and how the technique can help in evaluating the surface quality of substrates from different materials. The next paper from Kopin Corporation describes a new photoreflectance measurement configuration that is suitable for non-destructive measurements of HBT product wafers for quality testing purposes. Following this paper, a joint paper by Kyma Technologies, Dept. of Physics at Auburn Univ., and NRL will be presented. This paper will describe the developments in the production of 2” GaN substrates for optoelectronic and microelectronic applications, and the authors will present the results for AlGaN/GaN FET devices that were fabricated in the course of their studies. The final paper in this session is by Picogiga/Soitec and it addresses their latest results on “Engineered Substrates” fabricated by the Soitec “Smart Cut” technology for producing Si on poly-crystalline Si Carbide (SopSiC) substrates. Electrical results and manufacturing cost of SopSiC compared to SiC will also be presented.

SESSION 5: RELIABILITY & TEST

Chair:

Peter Ersland, M/A-COM, Inc.

We start this year’s reliability and test session with an invited paper from Skyworks, describing the implementation of a proactive problem prevention approach in pursuit of perfect product quality. Examples of steps taken so far to make “perfect quality” a reality will be presented. Next in the session is a contributed paper from Anadigics, discussing improvements made in their wafer level DC die sort test which have minimized the presence of test errors, resulting in improved test efficiency and faster resolution of true yield limiting issues identified at this test step. The session concludes with three contributed papers on the topic of MIM capacitor reliability: from TriQuint, we learn about experiments performed to characterize the sensitivity of various capacitor designs and configurations to Human Body Model ESD stress; from Northrop Grumman Space Technology, a paper discussing the reliability of capacitors built on top of backside vias; and from Northrop Grumman Electronic Systems, a presentation on the reliability of MIM capacitors for use with high voltage semiconductor technologies such as GaN HFETs and SiC Static Induction Transistors (SITs).

SESSION 6: PROCESS 1 – THIN FILMS & DRY ETCH

Chair:

Steve Mahon, TriQuint Semiconductor

A successful integrated circuit requires more technology than just a killer transistor. Passive components and integration issues may not be as sexy on a technology front but often have more impact on the overall effectiveness of the circuit than that of the active devices. This session offers four papers to look at both significant improvements in passive technology and GaN integration. With papers from Sony, TriQuint, North Carolina State University and the Tokyo Metropolitan University we get a real international flavor of the work occurring in these areas. The two passive papers show a couple of significant techniques to reduce chip size with exceptionally dense capacitors and high value resistor technologies. A 3.3fF/um², 40V MIM capacitor and a 1000 ohm/sq. thin film resistor are both significant jumps in the current state of compound semiconductor processing. Solutions for processing issues of the hottest emerging technology, GaN, are some of the most sought after information in our field. The last two papers provide insight into the etching techniques required for GaN and the effects and ameliorations of plasma induced damage. May the process gods be with you.

SESSION 7: OPTICAL & NOVEL DEVICES

Chair:

Jon Abrokwah, Freescale Semiconductor

This session includes four papers describing Optoelectronic Integrated Circuits on InP, the world’s first enhancement mode GaAs MOSFET, Flip Chip Assembled Integrated Passives and PHEMTs. In the first paper, which is invited, Richard Schneider et al. of Infinera Corporation review the evolution of discrete and integrated Optoelectronic IC on InP, and the unique challenges and requirements associated with manufacturing such components. Infinera demonstrates a 10-channel photonic IC with more than 40 distinct devices integrated, with data rate capability of 100 Gbs. Modern transistor technology is approaching the limit of fundamental electronic capabilities of silicon. Currently, high mobility materials, with high-k dielectrics, including III-Vs, are under consideration for future generation electronics at the end of the road of silicon. The second paper in this session from Freescale Semiconductor describes GaAs heterojunction MOSFETs, applying high-k dielectric insulators and high electron mobility channel layers. For over 40 years in the GaAs industry, a suitable gate insulating dielectric on GaAs with unpinned interface (like SiO₂ on silicon) has eluded the industry. The authors describe the breakthrough MBE-deposited high-k dielectrics on GaAs-based epitaxial layers with low interface state densities, and enhancement-mode MOSFETs with channel mobility of 6000 cm²/Vs and sheet carrier densities of 2-3 x 10¹² cm^-2. In the third paper, also from Freescale Semiconductor, Jon Abrokwah et al. describe flip-chip Low Band Harmonic Filter design based on GaAs Integrated Passive components for AMPS/GSM application. Harmonic Filters are used in radio modules, where size and cost continue to decrease. The authors realize 0.6 dB insertion loss in the pass band of 824 MHz to 915 MHz, and their EM simulation results are in good agreement with measured results. Finally, the fourth paper is a student paper from National Central University of Taiwan. The authors describe a flip-chip assembled PHEMT oscillator, whereby the flip chip approach offers design flexibility and low cost. The paper discusses the first K_a-band flip-chip PHEMT with feedback methodology. The 0.15mm gate PHEMT was flip-chipped to alumina substrate using Au/Zn bumps. EM simulation of the oscillation characteristics is in good agreement with measured results.

SESSION 8: PROCESS II: COST-REDUCED PROCESSING

Chair:

Pat Fowler, Anadigics, Inc.

Processing in today's cost conscious environment requires that process improvements and development are done with the cost impact in mind. This session features four papers that demonstrate this concept. The first paper from TriQuint describes their methodology for finding alternative chemistries to the chlorinated solvents that are used for photoresist removal and surface treatments. As environmental standards continue to be set higher, the costs of continuing to use cholrinated solvents can be, at the very least, lost revenue. An immediate cost savings is the result of the work reported in our paper from Skyworks. They present their work on finding the optimum thickness for the platinum diffusion barrier used in their Ti/Pt/Au metallizations. The last two papers approach the topic of cost from a yield improvement and throughput perspective. They deal with the dicing operation using lasers. The first one from ALSI discusses the requirements needed to adapt this technology. The second of the two describes how a water-jet-guided-laser is successfully set up to do damage-free dicing of SiC.

SESSION 9: HBT

Chair:

Noren Pan, Microlink Devices

There are four papers in the HBT session. The first paper by Sun et al. of Skyworks describes a high yield manufacturing process for InGaP BIFET. This structure is a combination of a heterojunction bipolar transistor and a MESFET. The MESFET provides an additional bias control for the power amplifier module. C-V measurements on the base/emitter junction provide a good characterization tool to measure the channel layer doping and thickness of the MESFET layer. An etch-stop layer provides additional control to maintain pinch-off voltage control. The second paper by Shokrani et al. of Anadigics presents the integration of an InGaP HBT and an AlGaAs PHEMT (InGaP plus). This integration offers increased functionality with one epitaxial layer structure. There does not appear to be any compromise in the performance and reliability characteristics between the integrated InGaP plus and their stand alone devices. The third paper by Y. Zeng et al. of Simon Fraser University presents a metamorphic InP/GaAsSb HBT grown on GaAs substrates. This type of HBT offers the staggered type II band lineup for improved breakdown voltages. Growth on GaAs substrates provides additional cost savings in comparison to growth on InP substrates. A DC current gain as high as 20 was observed in a 1 x 24 mm² device. F_tof 90 GHz and F_max of 100 GHz were measured, which is similar to that observed for this type of HBT grown on InP substrates. The fourth paper by B. C. Kung of the University of Illinois investigates the base collector parasitics for a multi-finger HBT. Four different types of base layer geometries were processed and measured. The differences in C_bc can be reflected in the measured F_max. The advantages of various designs for power and for speed are discussed. While multi-finger HBT’s are effective to realize higher power densities, this cannot be extended to W-band.

SESSION 10: PANEL SESSION

Chair:

Mike Barsky, Northrop Grumman ST

The Panel Session has returned, after a few years hiatus, to complement CS MANTECH’s popular Rump Sessions. This year’s panel session will focus on the future of Compound Semiconductors in the Wireless Communication Infrastructure. The panel will consist of industry experts from the commercial and military communication system integraters and manufacturers as well as CS integrated circuit manufacturers. We will discuss the future insertions for CS technology in communication platforms, and also where CS is losing its lead in currently held technology insertions. Will CS survive in mobile handsets? How is the infrastructure changing to the benefit or detriment of CS? Hear the answers to these questions and bring your most challenging and insightful questions for this panel of experts!

SESSION 11: RUMP SESSIONS

Chair:

Keith Salzman, TriQuint Semiconductor

As in the past, this year’s conference will include rump sessions featuring audience participation in a free exchange of ideas facilitated by knowledgeable moderators and free beer. These sessions provide a great opportunity to hear more about the issues affecting all of us and to share your own opinions and ideas. The topics this year were chosen to interest all who attend the conference, or many who attend, or at least a few other than the moderators:

1.	Recycling Texwipes? – How low can your fab costs go? Steve Mahon, TriQuint Semiconductor
2.	Foreign vs. native: What’s the best substrate technology for GaN devices? Drew Hanser, Kyma Technologies, Inc.
3.	Production vs. Development: Can manufacturing and R&D co-exist in the same fab? Oded Tal, Max International Engineering Group

All are invited and encouraged to attend one of these sessions for discussion that is often informative, sometimes frustrating, and always entertaining.

SESSION 12: HIGH VOLTAGE FETs

Chair:

Miro Micovic, HRL

GaN HFET technology has demonstrated superior RF power performance over mature GaAs pHEMT and Si LDMOS technologies, but until recently it was not considered as a serious contender due to poor device reliability and high fabrication cost. Reliability of GaN components is now improving rapidly, while cost is the only remaining barrier protecting incumbent technologies from the GaN challenge. Recent advances in high voltage GaAs FET technology could further delay widespread penetration of GaN parts. Papers presented in this session report latest advances in performance and reliability of GaN HFET’s and high voltage GaAs FET’s and also address large scale production of these components. An invited paper by Toshihide Kikkawa of Fujitsu will describe recent progress and future prospects of highly reliable GaN HFET’s for 3G wireless base station applications. Dr. Kikkawa will discuss approaches Fujitsu is taking to improve reliability and reduce cost of GaN components. Dr. Scott Sheppard will give an overview of GaN Class-E amplifier work done at Cree, Inc., and present remarkable performance figures recorded for their Class-E amplifiers (peak power of 63W with 75% of associated PAE at 2 GHz). Dr. Sarua of the University of Bristol will present novel thermal imaging technique using combined micro-Raman and IR approach to retrieve temperature of active III-V nitride devices. Dr. Saura’s talk will be of great interest to those interested in reliability of GaN devices, as it describes a novel technique for measurement of junction temperature. Dr. Mitani will describe development of mass production process for fabrication of high voltage GaAs FET’s and GaN HFET’s at Eudyna. Dr. Mitani will be able to answer tough GaN versus GaAs questions, as Eudyna is investing in both areas. Dr. Drinkwine will describe process for fabrication of high voltage GaAs MESFET’s developed at M/A-COM. According to Dr. Drinkwine, the M/A-COM high voltage MESFET is capable of 1.4 W/mm and 60% PAE at S-band operating from a 28 V supply and has predicted MTTF > 10⁶ hours at T_j = 150°C.

SESSION 13: PROCESS III – BACKSIDE

Chair:

Russ Westerman, Unaxis

High yield backside processes are critical to the profitability of any fab. Papers in this session address a number of issues in the different areas of backside processing. The first paper from Filtronics describes some of the challenges surrounding wafer bonding for thinned GaAs. The authors discuss challenges experienced during the transition from a wax based mounting process to an adhesive tape process. The second paper from Skyworks Solutions describes a backside yield problem that was traced to the street resist coat process. The authors track the problem back to the presence of bubbles in the resist and offer a solution to the problem of protecting features with steep topography. The third paper from Agilent Technologies discusses resist process optimisation for an ICP based InP via etch. The authors offer solutions to eliminate micromasking problems for processes using negative chemically amplified resists. The fourth paper in the session from TriQuint Semiconductor describes a GaAs via etch process that uses a RIE dry etch in conjunction with a wet finish etch to form through wafer vias. This process solves a lateral etching problem at the GaAs / gold interface as well as improving backside metal adhesion. The final paper of the session from Freescale Semiconductor discusses issues encountered in using a solder die attach process for high power GaAs devices. The paper describes adaptations to the metal stack to accommodate solder die attach as well as Freescale’s “edge seal” concept to handle sustained solder reflow temperatures.

SESSION 14: WIDE BANDGAP

Chair:

Shyh-Chiang Shen, Georgia Tech

This session will report on the development status of various wide-bandgap device technologies ranging from FET to BJT. An invited paper from Cree, Inc. will discuss the status and manufacturing issues of SiC-based power devices. 4H-SiC ion-implanted VJFET will be reported by Northrop Grumman Advanced Technology Laboratory that are capable of blocking 1.6 kV with optimized 2.1 mW-cm² specific-on resistance and >1200 V of breakdown voltage. A paper from the University of Colorado highlights the advancement of 4H-SiC BJT with f_Tof 7 GHz and f_MAX of 5 GHz – the highest RF data reported to date on SiC BJT. A MIS HEMT with AlN dielectric will be reported by authors from Nanjing Electronic Devices Institutes. At the closing of this session, a paper from Yole Development will present SiC, Sapphire, and GaN material development status and market trends in optoelectronics and RF applications.

SESSION 15: HIGH SPEED TECHNOLOGIES

Chair:

Roger Welser, Kopin Corp.

This session explores a variety of technologies employing indium-containing alloys to enhance the speed performance of III-V devices. To maximize indium concentration, metamorphic buffer layers are employed in the devices described in the first three presentations. The session begins with a paper from Northrop Grumman Space Technology describing their work on an InAs-based bipolar transistor technology for high-speed, low-power logic circuits. The second presentation from Rockwell Scientific and UC Santa Barbara highlights an InAs HEMT technology that was also partially developed under DARPA’s antimonide-based compound semiconductor (ABCS) program. A group from Hong Kong University of Science and Technology then describes their work using MOCVD in place of MBE growth technology to synthesize metamorphic buffer layers for InGaAs-based HEMT devices. The final two presentations in the session use pseudomorphic layers to increase the indium concentration in the channel layer of a HEMT device. A joint paper from the University of Notre Dame and MicroLink Devices details the temperature dependence of InGaAs pHEMTs with InGaP barriers. The session ends with a discussion of ultra high-speed InGaAs HEMT technology as a replacement for CMOS in logic applications.

SESSION 16: INTERACTIVE FORUM

Chairs:

Karen Renaldo, Northrop Grumman ES
Judy Kronwasser, NOVASIC

Following the tradition initiated in 1994, the Interactive Forum is a session devoted to promoting the open exchange of ideas and information. This session allows for informal discussions and face-to-face meetings between the authors and industry participants. During the Interactive Forum, all authors of presented papers will be available to answer questions and further discuss their technical results. In addition, this Forum will be the only time at the conference where papers that have been selected for the Interactive-only session will be displayed. This provides an opportunity for everyone to view and discuss these papers with the authors. Authors from Sessions 1 to 7 will be available during the first hour, and authors from Sessions 8 to 15 (excluding Sessions 10 and 11) will be available during the second hour. Authors for the interactive-only session, Session 16, will be available throughout the entire Interactive Forum Session. At the end of the session an award will be given to the author of the best poster. The winner will be chosen by votes of the attendees. A buffet luncheon will be provided, as well. The 2006 International Conference on Compound Semiconductor MANufacturing TECHnology cordially invites all attendees to visit this session, enjoy the refreshments, and meet your colleagues!

Special Thanks to our 2005 Exhibitors

Hotel Reservations
A block of rooms at the Fairmont Hotel Vancouver has been reserved for CS MANTECH participants and their guests. The special CS MANTECH room rate is $209.00 CDN (Canadian) for single or double occupancy. 17% in taxes will be added to these rates.

To make a hotel reservation, please register online through our website at: www.csmantech.org

Or complete the Reservation Form (at the end of this program) and return it directly to:

Fairmont Hotel Vancouver
Reservations Department
900 West Georgia Street
Vancouver, BC, V6C 2W6

Or FAX the Reservation Form to the Fairmont Reservations Department at: 604-662-1924

Or Reservations can be made by calling toll free: 1-800-441-1414 within North America. Please be sure to mention you are a CS MANTECH attendee.

We ask you to please support CS MANTECH and to enjoy all of the conference activities by staying at our official 2006 location, the Fairmont Hotel Vancouver. GaAs MANTECH, Inc. will be penalized if our room block is not filled.

Hotel reservations must be received BEFORE Thursday, March 23, 2006 to qualify for a room in the CS MANTECH room block. The discounted rate is subject to availability, so please MAKE YOUR RESERVATION EARLY! An advance deposit or credit card is required to hold your room.

Reservations received after THURSDAY, March 23, 2006 will be accepted on a space- and rate-availability basis.

If the room block fills prior to the cut off date, reservations will be accepted based on space and rate availability, so RESERVE EARLY!

Conference registration will open at the Vancouver Island Alcove Registration Desk on the Convention Floor of the Fairmont Hotel Vancouver on Sunday night and will be open Monday through Thursday during the following hours:

A Conference Attendee list will be available at the Information Center on Thursday, April 27.

Message BOARD
A Conference Message Board will be maintained at the Registration & Information Center during registration hours. Please advise callers who wish to reach you during the day to ask the hotel operator to deliver a message to the CS MANTECH Conference Registration Desk. Please check the message board periodically.

Speaker Preparation Room
The Garibaldi Room on the Convention Floor has been reserved for speaker preparation. This room will be open from 7:00 AM to 5:00 PM on Monday through Thursday, April 24-27. The room will be set up with appropriate previewing equipment.

Fairmont Hotel Vancouver
900 West Georgia Street
Vancouver, BC, V6C 2W6
Room Reservations: 1-800-441-1414 within North America
General Information: 604-684-3131
General Fax: 604-662-1924

The 2006 CS MANTECH conference will be held at the Fairmont Hotel Vancouver in British Columbia, Canada. Nestled between the majestic coastal mountains and the tides of the Pacific Ocean lies Vancouver, a city that attracts travelers from around the world who are drawn to its spectacular scenery and energetic lifestyle.
At the very heart is Vancouver's landmark, the Fairmont Hotel Vancouver. Like the city that surrounds it, it is rich in history, resplendent in natural beauty, vibrant and cosmopolitan

Vancouver's business, cultural and entertainment districts are at The Fairmont Hotel Vancouver's doorstep. Within its walls you will find the luxurious Absolute Spa, an exclusive Fairmont Gold floor, a state-of-the-art health club, award-winning restaurants and designer shops.
As the commercial center of British Columbia and one of North America’s largest ports, Vancouver is dynamic, modern, and growing at an unparalleled rate. In fact, statistics show that it’s the fastest-growing city on the continent and that it boasts an ethnically diverse population. In spite of such rapid growth, Vancouver is a picturesque town, surrounded by snow-capped peaks, Burrard Inlet, and English Bay. This spectacular setting is a mecca for outdoor enthusiasts, who also enjoy scenic getaways at Stanley Park, Grouse Mountain, and the area's various beaches. But Vancouver is chic as well as beautiful. Robson Street has been called the Rodeo Drive of Canada, and the city's cultural and performing arts are vibrant and sophisticated. In addition, Vancouver has become the third-largest film production center in North America – affectionately dubbed 'Hollywood North.'

Each of the Fairmont Hotel Vancouver’s 556 rooms and suites offers all the luxury and services of a world-class hotel with the elegance and charm of an English castle. Subtly included in every room are all the modern conveniences for business and leisure travelers alike. Luxuriously appointed rooms are spacious and comfortable and include Internet connections, two-line telephones, halogen lamps and coffee makers.

ENTERING CANADA
Canada welcomes more than 35 million visitors every year. For information on entering and visiting Canada, please visit the following Government of Canada website: www.cic.gc.ca/english/visit.

WEATHER
In late April, the typical highs are close to 15 degrees C (~60 degrees F) with lows around 7 degrees C (~55 degrees F). For up-to-the-minute weather information for Vancouver, visit www.theweathernetwork.com.

TRANSPORTATION TO THE HOTEL
The Fairmont Hotel Vancouver is easily reached in about 30 minutes from the Vancouver International Airport and in about 1 hour from the Peace Arch Border Crossing in Seattle, Washington.

Taxi: Taxis are available at the airport. Taxi rates from the airport to the Fairmont Hotel Vancouver are approximately $28.00 - $30.00 CDN.

Shuttle: An airport shuttle is available to and from the Vancouver International Airport. The rate to and from the Fairmont Hotel Vancouver is $12.00 CDN per person and reservations may be made at the information desk based in the airport. Return tickets may be purchased at the concierge desk in the hotel.

Car Rental: The approximate cost of a 7-day compact car rental is $250 CDN (~$215 US).

FINANCIAL ASSISTANCE
MANTECH strongly encourages and supports participation from academic delegates. Students and University Professors seeking financial assistance should contact Debora Green, the 2006 Conference Chair, by e-mail at student.aid@csmantech.org.

Registration Fees: Includes one printed copy and one CD of the Conference Digest, admission to all sessions, Exhibit Hall, International and Exhibits Receptions, Exhibit Luncheon, Panel & Rump Session Reception, Interactive Forum Reception, continental breakfasts and refreshment breaks. (All fees in US$.) EXCEPT FOR STUDENTS, CONFERENCE REGISTRATION FEE DOES NOT INCLUDE WORKSHOP REGISTRATION FEE.

* One-Day Registration can be used only once during the Conference. It includes a copy of the Conference Digest and CD. It does not include admission to the International Reception.

** Must fax proof of government employment if registering after March 25. Not for contractors.

*** Visit www.csmantech.org to order Conference Digests, Workshop Notes, or Workshop Videos for prior years.

Early Conference/Workshop Registration Cutoff Date March 25, 2006

Name:______________________________________________
Badge Name:________________________________________
Company:___________________________________________
Address:____________________________________________
City: ___________________ State: ______ Zip: ___________|Country: _____________
Phone: _______________________ Fax:__________________
Email:______________________________________________

Payment must accompany registration form. Registration forms sent without payment will not be accepted. Requests for refunds (less $25 processing fee) must be made to address above by Mar. 25. No refunds after Mar. 25, 2006.

Name on Card:___________________________
Card No:________________________________
Exp. Date:_______________________________

MANTECH Hotel
Registration Form
Register (use only 1 method)
Online at www.CSMANTECH.org
OR Either Fax OR Mail
to:

The Fairmont Hotel Vancouver
900 West Georgia Street
Vancouver, BC, V6C 2W6
Phone: 604-684-3131|
Fax: 604-662-1924

Please TYPE or PRINT all information clearly.

Room rate is valid for up to 2 guests/room. Add $30 CDN to room rate for each additional guest. There is no charge for children up to and including the age of 18 years who share with their parents. Maximum occupancy is 4 adults per room.

Hotel Group Rate Cutoff Date – March 23, 2006

If your requested room and bedding type are not available, an alternate will be assigned.

Fairmont Gold rooms and Suites may be available for $309.00 and $349.00, respectively, but are not reserved as part of the CS MANTECH room block.

Special Requests_______________________________________
____________________________________________________

All reservations must be guaranteed with a credit card, or a cash advance. A deposit equal to one night’s stay is required to hold each reservation. The deposit is refundable if notice is received at least forty-eight (48) hours prior to scheduled check-in. One night’s room and tax will be charged if cancelled less than 48 hours prior to arrival.

Special Thanks to our 2005 Exhibitors

For Advanced Conference Registration, complete the enclosed Registration Form at the end of this Advance Program and return with payment by March 25 to:

CS MANTECH Conference
c/o Lucky Gold Co.
4126 Crescent Drive
St. Louis, MO, USA 63129
Phone:    (314) 894-0080
Fax:         (314) 894-0450
Email:      LLLCPA@aol.com

Early Conference/Workshop Registration Cutoff Date March 25, 2006

Please TYPE or PRINT all information clearly.

Hotel Group Rate Cutoff Date – March 23, 2006

Special Thanks to our 2005 Exhibitors

For Advanced Conference Registration, complete the enclosed Registration Form at the end of this Advance Program and return with payment by March 25 to:

CS MANTECH Conference c/o Lucky Gold Co. 4126 Crescent Drive St. Louis, MO, USA 63129 Phone: (314) 894-0080 Fax: (314) 894-0450 Email: LLLCPA@aol.com

Early Conference/Workshop Registration Cutoff Date March 25, 2006

Please TYPE or PRINT all information clearly.

Hotel Group Rate Cutoff Date – March 23, 2006

CS MANTECH Conference
c/o Lucky Gold Co.
4126 Crescent Drive
St. Louis, MO, USA 63129
Phone: (314) 894-0080
Fax: (314) 894-0450
Email: LLLCPA@aol.com